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1 www.pericom.com pi6c49019 rev . b 06/25/13 pi6c49019 block diagram description the new pi6c49019 is a high integration clock generator intended for all kinds of embedded applications and networking application with pcie interface. the device is the most cost effective way to generate multi-frequencies and multi-outputs clocks from a 25mhz crystal and reference clock. the device can generate four pairs low power 100mhz hcsl outputs for pcie, one single-ended 25mhz and 125 mhz output, one single-ended 48mhz and 19.2 mhz output, and one single-ended 33.33 mhz or 67.33mhz output with spread spectrum. using a serially programmable smbus interface, the pi6c49019 incorporates spread spectrum modulation on the four 100 mhz pci-express outputs with -0.5% down spread and the 33.33 mhz/67.33 mhz output with down spread. low power networking clock generator features ? ? 3.3v supply voltage ? ? 25mhz xtal or reference clock input ? ? output ? 4x100mhz hcsl pcie clock outputs with integrated series termination resistors, spread spectrum capability on all 100mhz pcie clock outputs with -0.5% down spread. ? 1x single-ended 33.33mhz or 67.33mhz output with spread spectrum capability ? 1x single-ended 125mhz output for gigabit ethernet ? 1x single-ended 25mhz ? 1x single-ended 48mhz ? 1x single-ended 19.2mhz ? ? packaging (pb free and green) : 48-pin tssop (a) ? ? industrial temperature support clock b uffer/ crys tal osci lla tor pll clock synthesis, dividers, buffers and configuration logic x1 /iclk x2 sc lk sd ata 25 mhz crystal or clock inp ut gnd ex tern al ca ps re qu ir ed with crystal for accurate t uni ng of the clock 100 mhz pci e0 125 mhz/ref vdd p d_r eset 100 mhz pci e1 100 mhz pci e2 100 mhz pci e3 vddo2 48 mhz 19 .2 mhz 25 mhz 33.33 mh z/ 67.3 3 mhz 13-0103
2 www.pericom.com pi6c49019 rev . b 06/25/13 pin description pin# pin name pin ty pe pin description 1 vdd power 3.3v supply pin 2 cdd input input pin for of chip bypass capacitor. connect to 0.01 f capacitor 3 pcie2n output diferential 100 mhz hcsl pci express clock output 4 pcie2 output diferential 100 mhz hcsl pci express clock output 5 vdd power 3.3v supply pin 6 gnd power ground 7 vdd power 3.3v supply pin 8 pcie3n output diferential 100 mhz hcsl pci express clock output 9 pcie3 output diferential 100 mhz hcsl pci express clock output 10 gnd power ground 11 vdd power 3.3v supply pin 12 sclk input smbus clock input 13 sdata i/o smbus data input 14 gnd power ground 15 33m/67m output 33.33 mhz or 67.33 mhz lvcmos output. tri-stated with a weak pull-down when disabled. pin list 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vdd cdd pcie0n pcie0 gnd gnd vdd sclk sdata gnd vdd vdd vdd 33m/67m gnd gnd pd_reset 25m 125m/ref pcie1n pcie2 pcie2n vdd pcie3n pcie3 gnd vddo2 nc vdd x2 x1 pcie1 nc nc gnd vdd gnd gnd vdd 48m vdd vdd gnd vdd 19m vdd nc nc pi6c49019 low power networking clock generator 13-0103
3 www.pericom.com pi6c49019 rev . b 06/25/13 pin list pin# pin name pin ty pe pin description 16 vdd power 3.3v supply pin 17 vdd power 3.3v supply pin 18 gnd power ground 19 19m output 19.2 mhz lvcmos output. tri-state with weak pull- down when disabled 20 vdd power 3.3v supply pin 21 gnd power ground 22 nc - - 23 nc - - 24 pd_reset input global reset input powers down plls plus tri-states outputs and sets the i2c tables to their default state when pulled low. controlled by external por. 25 x1 xi crystal input. connect to 25 mhz fundamental mode crystal or clock 26 x2 xo crystal output. connect to 25 mhz fundamental mode crystal. float for clock input 27 vdd power 3.3v supply pin 28 nc - - 29 nc - - 30 nc - - 31 vddo2 power 125 mhz output supply voltage. connect to +2.5 v 32 125m/ref output 125 mhz or 25 mhz reference +2.5 v lvcmos out - put. tri-stated with a weak pull-down when disabled 33 25m output 25 mhz +2.5 lvcmos output. tri-stated with a weak pull-down when disabled 34 gnd power ground 35 vdd power 3.3v supply pin 36 gnd power ground 37 vdd power 3.3v supply pin 38 gnd power ground 39 48m output 48 mhz lvcmos output. tri-state with weak pull- down when disabled 40 vdd power 3.3v supply pin 41 gnd power ground 42 vdd power 3.3v supply pin 43 pcie0n output diferential 100 mhz hcsl pci express clock output 44 pcie0 output diferential 100 mhz hcsl pci express clock output 45 pcie1 output diferential 100 mhz hcsl pci express clock output 46 pcie1n output diferential 100 mhz hcsl pci express clock output 47 vdd power 3.3v supply pin 48 gnd power ground pi6c49019 low power networking clock generator 13-0103
4 www.pericom.com pi6c49019 rev . b 06/25/13 selection table 1 C 33m/67m spread spectrum ss1 ss0 ssc 0 0 no spread 0 1 down -0.5% 1 0 down -0.75% 1 1 down -1.00% selection table 2 C 125 mhz / 25 mhz frequency selection table sel output 0 ref 1 125 mhz notes: vdd and gnd pins layout guide 1. small value decoupling caps. (0.1uf, 1uf, and 2.2uf) should be placed close each vdd pin or its via 2. connect all gnd pins to package thermal pad which must be connected to the gnd plane for better thermal distribution and signal conducting with reason - able via count (>8) pi6c49019 low power networking clock generator 13-0103
5 www.pericom.com pi6c49019 rev . b 06/25/13 serial data interface (smbus) pi6c49019 is a slave only smbus device that supports indexed block read and indexed block write protocol using a single 7-bit ad - dress and read/write bit as shown below. address assignment a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 0 0 1 0/1 how to write 1 bit 8 bits 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit d2h ack register offset ack byte count = n ack data byte 0 ack data byte n - 1 ack stop bit note: 1. register of fset for indicating the starting register for indexed block write and indexed block read. byte count in write mode cannot be 0. byte 0: spread spectrum control register bit description type power up condition output(s) affected notes 7 spread select for 100mhz hcsl pci-express clocks rw 0 all 100mhz hcsl pci-express outputs 0=spread off 1=-0.5% down 6 enables hardware or software control of oe bits (see byte 0-bit 6 and bit 5 functionality table) rw 0 pd_reset , bit 5 0 = hardware cntl 1 = software ctrl 5 software pd_reset bit. enables or disables all outputs. (see byte 0-bit 6 and bit 5 functionality table) rw 1 all outputs 0 = disabled 1 = enabled 4 spread select for 33.33/67.33 mhz s1 rw 0 33mhz lvcmos output pin 15 see table1 on page4 3 spread select for 33.33/67.33 mhz page 4 s0 rw 0 2 oe for single-ended 25 mhz rw 1 25m 0 = disabled 1 = enabled 1 frequency select bit rw 1 125m/ref 0 = ref 1 = 125m 0 oe for single-ended 125 mhz/ref rw 1 single-ended 125mhz/ref pin 30 0 = disabled 1 = enabled how to read (m: abbreviation for master or controller; s: abbreviation for slave/clock) 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 8 bits 1 bit 1 bit m: start bit m: send "d2h" s: sends ack m: send starting databyte location: n s: sends ack m: start bit m: send "d3h" s: sends ack s: sends # of data bytes that will be sent: x m: sends ack s: sends start - ing data byte n m: sends ack s: sends data byte n+x- 1 m: not ac - knowl - edge m: stop bit pi6c49019 low power networking clock generator 13-0103
6 www.pericom.com pi6c49019 rev . b 06/25/13 byte 1: control register bit description type power up condi - tion output(s) affected notes 7 oe for 33.33/67.33 mhz output rw 1 33/67m 1 = enabled 0 = disabled 6 33.33/67.33 mhz select rw 0 33/67m 0 = 67.33 mhz 1 = 33.33 mhz 5 to 0 reserved r - - - bit description type power up condi - tion output(s) affected notes 7 to 0 reserved r - - - byte 2: control register byte 3: spread spectrum control register bit description type power up condition output(s) affected notes 7 reserved rw 0 - - 6 oe for 48 mhz output rw 0 48m 1 = enabled 0 = disabled 5 oe for 100 mhz pci-express output pcie3 rw 1 100mhz hcsl pci-express output pcie3 1 = enabled 0 = disabled 4 oe for 100 mhz pci-express output pcie2 rw 1 100mhz hcsl pci-express output pcie2 1 = enabled 0 = disabled 3 oe for 19.2 mhz output rw 0 19m 1 = enabled 0 = disabled 2 oe for 100 mhz pci-express output pcie1 rw 1 100mhz hcsl pci-express output pcie1 1 = enabled 0 = disabled 1 oe for 100 mhz pci-express output pcie0 rw 1 100 mhz pci-express output pcie0 1 = enabled 0 = disabled 0 reserved r - - - byte 0: bit 6 and bit 5 functionality bit 6 bit 5 description 0 x ( pd_reset = "h" will enable all outputs; smbus cannot control each output.) 1 0 disables all outputs and tri-states the outputs, pd_reset hw pin/signal = do not care 1 1 enable outputs according to the smbus default values; smbus can control each output. pd_reset hw pin/signal = do not care pi6c49019 low power networking clock generator 13-0103
7 www.pericom.com pi6c49019 rev . b 06/25/13 byte 5: control register bit description type power up condition output(s) affected notes 7 revision id bit 3 r 0 - - 6 revision id bit 2 r 0 - 5 revision id bit 1 r 0 - 4 revision id bit 0 r 0 - 3 vendor id bit 3 r 0 - 2 vendor id bit 2 r 0 - 1 vendor id bit 1 r 0 - 0 vendor id bit 0 r 0 - bit description type power up condi - tion output(s) affected notes 7 to 0 reserved r - - - byte 6: control register bit description type power up condi - tion output(s) affected notes 7 to 0 reserved r - - - byte 4: control register pi6c49019 low power networking clock generator 13-0103
8 www.pericom.com pi6c49019 rev . b 06/25/13 maximum supply voltage, v dd .............................................................. 7v all inputs and outputs ................................................ C0.5v to v dd +0.5v ambient operating temperature ....................................... C40c to +85c storage temperature ........................................................ C65c to +150c junction temperature ........................................................................ 125 c peak soldering temperature .............................................................. 260c esd protection (hbm).................................................................... 2000v note: stresses above the ratings listed below can cause permanent damage to the pi6c49019. these ratings, which are standard values for pericom commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifcations is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) dc electrical characteristics unless otherwise specifed, v dd =3.3v 10%, v ddo2 =2.5v,ambient temperature C40c to +85c parameter symbol conditions min typ max units operating supply voltage v dd 3.0 3.3 3.6 v output supply voltage v ddo2 2.25 2.5 3.6 input high voltage v ih x1/sclk, sdata, pd_reset 2 v dd input low voltage v il x1/sclk, sdata, pd_reset C 0.3 0.8 operating supply current i dd no load, all supply pins, pd_reset = 1 90 100 ma idd at output disable condition pd_reset = 0 6 short circuit current i os single-ended clocks 35 internal pull-up/pull- down resistor r pu /r pd pd_reset 240 k? all single-ended clocks 110 input capacitance c in all input pins 6 pf recommended operation conditions parameters min. typ. max. units ambient operating temperatur -40 +85 c power supply voltage (measured in respect to gnd) +3.0 3.3 +3.6 v output supply voltage, v ddo2 +2.25 +3.6 v minimum pulse width of pd_reset input 100 ns pi6c49019 low power networking clock generator 13-0103
9 www.pericom.com pi6c49019 rev . b 06/25/13 electrical characteristics - single-ended unless otherwise specifed, v dd =3.3v 10%, v ddo2 =2.5v, ambient temperature C40c to +85c parameter symbol conditions min typ max units input clock frequency f in 25 mhz output frequency error 0 ppm output rise time t or 20% to 80% 1 0.5 1 ns 0.7 v to 1.7v 125 mhz 0.4 output fall time t of 80% to 20% 1 0.5 1 output clock duty cycle measured at v dd/2 45 50 55 % high-level output voltage v oh i oh = -4ma vdd-0.4 high-level output voltage v oh i oh = -8ma 2.4 v low-level output volt - age v ol i ol = 8ma 0.4 v peak-to-peak jitter 33mhz clock output 150 ps 125mhz clock output 100 cycle-to-cycle jitter 125mhz clock output 1 100 33/67mhz clock output 1,2 100 clock stabilization time from power up pd_reset goes high to 1% of fnal frequency 3 10 ms note 1: cl = 15 pf note 2: cycle-to-cycle jitter is measured at 25c. note 3: spread off. pi6c49019 low power networking clock generator 13-0103
10 www.pericom.com pi6c49019 rev . b 06/25/13 electrical characteristics - 100 mhz differential push-pull outputs unless otherwise specifed, v dd =3.3v 10%, ambient temperature C40c to +85c parameter symbol conditions min ty p max units output frequency 100 mhz cycle-to-cycle jitter t cc/jitter 150 ps peak-to-peak phase jitter using fxed-flter clock recovery function 86 pcie 2.0 rms phase jitter j rm52.0 pcie 2.0 test method @ 100 mhz output 3.1 ps spread range -0.5 0 % spread rate 32 khz duty cycle t dc 45 50 55 % clock stabilization from power up 3.5 ms rising edge rate note3, 4 0.6 4.0 v/ns falling edge rate note3, 4 0.6 4.0 v/ns rise-fall matching note3, 11 20 % output skew t oskew v t = 50%(measurement threshold), intra-pair skew 50 ps v t = 50%(measurement threshold), inter-pair skew 200 ps clock source dc impedance(zo) z c-dc 17 ? high-level output volt age v ol note2 (rs = 33ohm) 0.65 0.71 0.85 v low-level output voltage v oh -0.20 0 0.05 absolute crossing point volt age v cross note2, 5, 6 0.25 0.55 v variation of v cross over all rising clock edges v cross delta note2, 5, 8 140 mv average clock period accuracy t period avg note3, 9, 10 -300 2800 ppm absolute period (including jitter and spread spectrum) t period abs note3, 7 9.847 10.203 ns notes: 2. measurement taken from a single-ended waveform. 3. measurement taken from a differential waveform. 4. measured from -150 mv to +150 mv on the differential waveform. the signal is monotonic through the measurement region for rise and fall time. the 300 mv measurement window is centered on the differential zero crossing. 5. measured at crossing point where the instantaneous voltage value of the rising edge of 100m+ equals the falling edge 100m C . 6. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. pi6c49019 low power networking clock generator 13-0103
11 www.pericom.com pi6c49019 rev . b 06/25/13 thermal characteristics parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 60.3 c/w ja 1 m/s air fow 53 c/w ja 3 m/s air fow 50 c/w thermal resistance junction to case jc 27.7 c/w thermal resistance junction to top of case jt still air 1.2 c/w jt 1 m/s air fow 1.5 c/w jt 3 m/s air fow 2.0 c/w 7. defnes as the absolute minimum or maximum instantaneous period. this includes cycle-to-cycle jitter, relative ppm tolerance, and spread spectrum modulation. 8. defned as the total variation of all crossing voltages of rising 100m+ and falling 100m C . 9. refer to section 4.3.2.1 of the pci express base specifcation, revision 1.1 for information regarding ppm considerations. 10. ppm refers to parts per million and is a dc absolute period accuracy specifcation. 1 ppm is 1/1,000,000th of 100 mhz exactly or 100 hz. for 300 ppm there is an error budget of 100hz/ppm * 300 ppm = 30 khz. the period is measured with a frequency counter with measurement window set at 100 ms or greater. with spread spectrum turned off the error is less than 300 ppm. with spread spectrum turned on there is an additional +2500 ppm nominal shift in maximum period resulting from the -0.5% down spread. 11. matching applies to rising edge rate for pcie and falling edge rate for pcien. it is measured using a 75 mv window centered on the median cross point where pcie rising meets pcien falling. the median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. the rising edge rate of pcie should be compared to the falling edge rate of pcien. the maximum allowed difference should not exceed 20% of the slowest edge rate. notes (continued) pi6c49019 low power networking clock generator 13-0103
12 www.pericom.com pi6c49019 rev . b 06/25/13 c1 27pf crystal?(c l? =?18pf) c2 27pf xtal_in xtal_out saronix-ecera fl2500047 application notes crystal circuit connection te following diagram shows pi6c49019 crystal circuit connection with a parallel crystal. for the cl=18pf crystal, it is suggested to use c1= 27pf, c2= 27pf. c1 and c2 can be adjusted to fne tune to the target ppm of crystal oscillator according to diferent board layouts. crystal oscillator circuit recommended crystal specification pericom recommends: a) fl2500047, smd 3.2x2.5(4p), 25m, cl=18pf, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/fl.pdf b) fy2500081, smd 5x3.2(4p), 25m, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf x1 x2 cb c1 c2 cj rd rf cb pseudo sine cj cl= crystal spec. loading cap. cj = chip in/output cap. (3~5pf) cb = pcb trace/via cap. (2~4pf) c1,2 = load cap. components rd = drive level res. (100ohm) asic final choose/trim c1=c2=2 *cl - (cb +cj) for the target +/-ppm example: c1=c2=2*(18pf) ? (4pf+5pf)=27pf pi6c49019 low power networking clock generator 13-0103
13 www.pericom.com pi6c49019 rev . b 06/25/13 decoupling capacitors decoupling capacitors of 0.01 f should be connected between vdd and gnd as close to the device as possible. do not share ground vias between components. route power from power source through the capacitor pad and then into pi6c49019 pin. output termination te pci-express diferential clock outputs of the pi6c49019 are push-pull and require an external series resistor. tese resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. te pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the fer - rite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from pi6c49019.tis includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. pi6c49019 low power networking clock generator 13-0103
14 www.pericom.com pi6c49019 rev . b 06/25/13 pci-express layout guidelines common recommendations for differential routing dimension or value unit figure notes l1 length, route as non-coupled 50 ohm trace. 0.5 max inch 1,2 l2 length, route as non-coupled 50 ohm trace. 0.2 max inch 1,2 l3 length, route as non-coupled 50 ohm trace. 0.2 max inch 1,2 r s 33 ohm 1,2 down device differential routing dimension or value unit figure notes l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1 l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1 l1 l1? l2? l2 l4 l4? rs rs output buffer pci express board down device ref_clk input l1 l1? l2? l2 l4 l4? rs rs output buffer pci-express add-in board ref_clk input figure 2: pci-express connector routing figure 1: down device routing pi6c49019 low power networking clock generator 13-0103
15 www.pericom.com pi6c49019 rev . b 06/25/13 rs 33? 5% rs 33? 5% 2pf 5% 2pf 5% clock# clock tla tlb pi6c49019 )ljxuh&rq?jxudwlrq7hvw/rdg%rdug7huplqdwlrq pi6c49019 low power networking clock generator 13-0103
16 www.pericom.com pi6c49019 rev . b 06/25/13 ordering information (1-3) ordering code package code package description PI6C49019AIE a 48-pin, pb-free & green, tssop, (a48) notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. adding an x suffx = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com 1 .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc document control no. pd - 1501 revision: g date: 03/09/05 note: 1. controlling dimensions in millimeters. 2. ref: jedec mo-153f/ed 3. dimension does not include mold ? ash, protrusions or gate burrs. mold ? ash, protru- sions and gate burrs shall not exceed 0.15mm per side. 4. dimension does not include interlead ? ash or protrusion. interlead ? ash or protrusion shall not exceed 0.25mm per side. description: 48-pin 240-mil wide tssop package code: a pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com see note 3 see note 4 note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php all trademarks are property of their respective owners. pi6c49019 low power networking clock generator 13-0103

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